slas/rv64.inc

%def: x0 0
%def: x1 1
%def: x2 2
%def: x3 3
%def: x4 4
%def: x5 5
%def: x6 6
%def: x7 7
%def: x8 8
%def: x9 9
%def: x10 10
%def: x11 11
%def: x12 12
%def: x13 13
%def: x14 14
%def: x15 15
%def: x16 16
%def: x17 17
%def: x18 18
%def: x19 19
%def: x20 20
%def: x21 21
%def: x22 22
%def: x23 23
%def: x24 24
%def: x25 25
%def: x26 26
%def: x27 27
%def: x28 28
%def: x29 29
%def: x30 30
%def: x31 31

%def: zero x0
%def: ra x1
%def: sp x2
%def: gp x3
%def: tp x4
%def: t0 x5
%def: t1 x6
%def: t2 x7
%def: s0 x8
%def: s1 x9
%def: a0 x10
%def: a1 x11
%def: a2 x12
%def: a3 x13
%def: a4 x14
%def: a5 x15
%def: a6 x16
%def: a7 x17

%def: fp s0

%macro: rv.rtype op, dst, fn3, src1, src2, fn7
	data32 (((((op | (dst << 7)) | (fn3 << 12)) | (src1 << 15)) | (src2 << 20)) | (fn7 << 25))
%endmacro

%macro: rv.itype op, dst, fn3, src1, imm
	data32 ((((op | (dst << 7)) | (fn3 << 12)) | (src1 << 15)) | (imm << 20))
%endmacro

%macro: rv.stype op, imm04, fn3, src1, src2, imm511
	data32 (((((op | (imm04 << 7)) | (fn3 << 12)) | (src1 << 15)) | (src2 << 20)) | (imm511 << 25))
%endmacro

%macro: rv.stype op, imm, fn3, src1, src2
	rv.stype op, (imm & 0x1F), fn3, src1, src2, (imm >> 5)
%endmacro

%macro: rv.utype op, dst, imm
	data32 ((op | (dst << 7)) | (imm << 12))
%endmacro

%macro: rv.btype op, imm, fn3, src1, src2
	rv.stype op, ((((imm >> 12) << 11) | (imm & 0x3FE)) | ((imm >> 11) & 1)), fn3, src1, src2
%endmacro

%macro: rv.jtype op, dst, imm
	rv.utype op, dst, ((((imm & (1 << 20)) | (((imm >> 1) & 0x3FF) << 10)) | (((imm >> 11) & 1) << 8)) | ((imm >> 12) & 0xFF))
%endmacro

%def: OP_IMM 0b0010011
%def: OP_ALU 0b0110011

%def: FN3_ADD	0b000
%def: FN3_SLL	0b001
%def: FN3_SLT	0b010
%def: FN3_SLTU	0b011
%def: FN3_XOR	0b100
%def: FN3_SRL	0b101
%def: FN3_OR	0b110
%def: FN3_AND	0b111

%macro: addi dst, src, n
	rv.itype OP_IMM, dst, FN3_ADD, src, n
%endmacro
%macro: slti dst, src, n
	rv.itype OP_IMM, dst, FN3_SLT, src, n
%endmacro
%macro: sltiu dst, src, n
	rv.itype OP_IMM, dst, FN3_SLTU, src, n
%endmacro
%macro: xori dst, src, n
	rv.itype OP_IMM, dst, FN3_XOR, src, n
%endmacro
%macro: ori dst, src, n
	rv.itype OP_IMM, dst, FN3_OR, src, n
%endmacro
%macro: andi dst, src, n
	rv.itype OP_IMM, dst, FN3_AND, src, n
%endmacro
%macro: slli dst, src, n
	rv.itype OP_IMM, dst, FN3_SLL, src, n
%endmacro
%macro: srli dst, src, n
	rv.itype OP_IMM, dst, FN3_SRL, src, n
%endmacro

%macro: add dst, src1, src2
	rv.stype OP_ALU, dst, FN3_ADD, src1, src2, 0b0000000
%endmacro
%macro: sub dst, src1, src2
	rv.stype OP_ALU, dst, FN3_ADD, src1, src2, 0b0100000
%endmacro
%macro: sll dst, src1, src2
	rv.stype OP_ALU, dst, FN3_SLL, src1, src2, 0b0000000
%endmacro
%macro: srl dst, src1, src2
	rv.stype OP_ALU, dst, FN3_SRL, src1, src2, 0b0000000
%endmacro
%macro: sra dst, src1, src2
	rv.stype OP_ALU, dst, FN3_SRL, src1, src2, 0b0100000
%endmacro
%macro: slt dst, src1, src2
	rv.stype OP_ALU, dst, FN3_SLT, src1, src2, 0b0000000
%endmacro
%macro: sltu dst, src1, src2
	rv.stype OP_ALU, dst, FN3_SLTU, src1, src2, 0b0000000
%endmacro
%macro: or dst, src1, src2
	rv.stype OP_ALU, dst, FN3_OR, src1, src2, 0b0000000
%endmacro
%macro: and dst, src1, src2
	rv.stype OP_ALU, dst, FN3_AND, src1, src2, 0b0000000
%endmacro
%macro: xor dst, src1, src2
	rv.stype OP_ALU, dst, FN3_XOR, src1, src2, 0b0000000
%endmacro

%macro: snez dst, src2
	sltu dst, zero, src2
%endmacro

%macro: lb dst, off(src)
	rv.itype 0b0000011, dst, 0b000, src, off
%endmacro
%macro: lbu dst, off(src)
	rv.itype 0b0000011, dst, 0b100, src, off
%endmacro
%macro: lh dst, off(src)
	rv.itype 0b0000011, dst, 0b001, src, off
%endmacro
%macro: lhu dst, off(src)
	rv.itype 0b0000011, dst, 0b101, src, off
%endmacro
%macro: lw dst, off(src)
	rv.itype 0b0000011, dst, 0b010, src, off
%endmacro
%macro: ld dst, off(src)
	rv.itype 0b0000011, dst, 0b011, src, off
%endmacro

%macro: sb src1, off(src2)
	rv.stype 0b0100011, off, 0b000, src2, src1
%endmacro
%macro: sh src1, off(src2)
	rv.stype 0b0100011, off, 0b001, src2, src1
%endmacro
%macro: sw src1, off(src2)
	rv.stype 0b0100011, off, 0b010, src2, src1
%endmacro
%macro: sd src1, off(src2)
	rv.stype 0b0100011, off, 0b011, src2, src1
%endmacro


%macro: jal dst, imm
	rv.jtype 0b1101111, dst, imm
%endmacro
%macro: jalr dst, src, imm
	rv.itype 0b1100111, dst, 0b000, src, imm
%endmacro
%macro: jalr src
	jalr x1, src, 0
%endmacro
%macro: j imm
	jal zero, imm
%endmacro

%macro: beq src1, src2, imm
	rv.btype 0b1100011, imm, 0b000, src1, src2
%endmacro
%macro: bne src1, src2, imm
	rv.btype 0b1100011, imm, 0b001, src1, src2
%endmacro

%macro: beqz src, imm
	beq src, zero, imm
%endmacro

%macro: sltiu dst, src, imm
	rv.itype 0b0010011, dst, 0b011, src, imm
%endmacro
%macro: seqz dst, src
	sltiu dst, src, 1
%endmacro

%macro: lui dst, imm
	rv.utype 0b0110111, dst, imm
%endmacro

%macro: li dst, imm
	lui dst, (imm >> 12)
	addi dst, dst, (imm & 0xFFF)
%endmacro
%macro: la dst, imm
	lui dst, (imm >> 12)
	addi dst, dst, (imm & 0xFFF)
%endmacro

%macro: call imm
	jal x1, imm
%endmacro
%macro: ret
	jalr x0, x1, 0
%endmacro

%macro: mv dst, src
	addi dst, src, 0
%endmacro

# RV32M
%macro: mul dst, src1, src2
	rv.rtype 0b0110011, dst, 0b000, src1, src2, 0b0000001
%endmacro
%macro: div dst, src1, src2
	rv.rtype 0b0110011, dst, 0b100, src1, src2, 0b0000001
%endmacro
%macro: divu dst, src1, src2
	rv.rtype 0b0110011, dst, 0b101, src1, src2, 0b0000001
%endmacro
%macro: rem dst, src1, src2
	rv.rtype 0b0110011, dst, 0b110, src1, src2, 0b0000001
%endmacro
%macro: remu dst, src1, src2
	rv.rtype 0b0110011, dst, 0b111, src1, src2, 0b0000001
%endmacro

# RV64I
%macro: addiw dst, src, imm
	rv.itype 0b0011011, dst, FN3_ADD, src, imm
%endmacro

%macro: sext.w dst, src
	addiw dst, src, 0
%endmacro

;rv.itype OP_IMM, 8, FN3_ADD, 8, 8
;addi 8, 8, 8
;ld dst, 8(8)

%macro: .global n
	data.symbol n, 4096
%endmacro