slkern/riscv.S

169 lines
2.0 KiB
ArmAsm

// TODO: CHECK/REPLACE/UPDATE OLD CODE (this file is based on xv6, although it was converted from inline functions to plain assembly)
.option norvc
.text
.globl r_mhartid
r_mhartid:
csrr a0, mhartid
ret
.globl r_mstatus
r_mstatus:
csrr a0, mstatus
ret
.globl w_mstatus
w_mstatus:
csrw mstatus, a0
ret
.globl w_mepc
w_mepc:
csrw mepc, a0
ret
.globl r_sstatus
r_sstatus:
csrr a0, sstatus
ret
.globl w_sstatus
w_sstatus:
csrw sstatus, a0
ret
.globl r_sip
r_sip:
csrr a0, sip
ret
.globl w_sip
w_sip:
csrw sip, a0
ret
.globl r_sie
r_sie:
csrr a0, sie
ret
.globl w_sie
w_sie:
csrw sie, a0
ret
.globl r_mie
r_mie:
csrr a0, mie
ret
.globl w_mie
w_mie:
csrw mie, a0
ret
.globl w_sepc
w_sepc:
csrw sepc, a0
ret
.globl r_sepc
r_sepc:
csrr a0, sepc
ret
.globl r_medeleg
r_medeleg:
csrr a0, medeleg
ret
.globl w_medeleg
w_medeleg:
csrw medeleg, a0
ret
.globl r_mideleg
r_mideleg:
csrr a0, mideleg
ret
.globl w_mideleg
w_mideleg:
csrw mideleg, a0
ret
.globl w_stvec
w_stvec:
csrw stvec, a0
ret
.globl r_stvec
r_stvec:
csrr a0, stvec
ret
.globl r_stimecmp
r_stimecmp:
csrr a0, 0x14d
ret
.globl w_stimecmp
w_stimecmp:
csrw 0x14d, a0
ret
.globl r_menvcfg
r_menvcfg:
csrr a0, 0x30a
ret
.globl w_menvcfg
w_menvcfg:
csrw 0x30a, a0
ret
.globl w_pmpcfg0
w_pmpcfg0:
csrw pmpcfg0, a0
ret
.globl w_pmpaddr0
w_pmpaddr0:
csrw pmpaddr0, a0
ret
.globl w_satp
w_satp:
csrw satp, a0
ret
.globl r_satp
r_satp:
csrr a0, satp
ret
.globl r_scause
r_scause:
csrr a0, scause
ret
.globl r_stval
r_stval:
csrr a0, stval
ret
.globl w_mcounteren
w_mcounteren:
csrw mcounteren, a0
ret
.globl r_mcounteren
r_mcounteren:
csrr a0, mcounteren
ret
.globl r_time
r_time:
csrr a0, time
ret
.globl intr_on
intr_on:
csrr a5, sstatus
ori a5,a5,2
csrw sstatus, a5
ret
.globl intr_off
intr_off:
csrr a5, sstatus
andi a5,a5,-3
csrw sstatus, a5
ret
.globl intr_get
intr_get:
csrr a0, sstatus
bexti a0,a0,1
ret
.globl r_sp
r_sp:
mv a0, sp
ret
.globl w_tp
w_tp:
mv tp, a0
ret
.globl r_ra
r_ra:
mv a0, ra
ret
.globl sfence_vma
sfence_vma:
sfence.vma zero, zero
ret