Partial maths fix, div/rem operators now work for 32/64 bit code (should be mirrored in fossil...). Some issues may still remain with different combinations of types/signednesses/operators and won't be fixed on x86 as pervasively as on RV64.

This commit is contained in:
2025-08-26 18:05:30 +10:00
parent 7f74463109
commit 1e92a65aaa

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@@ -1826,7 +1826,9 @@ static void ccb_target_gen_binary_arithmetic_integer(ccb_t* ccb, ccb_ast_t* ast)
ccb_target_gen_emit("signx64x32 r0");
}
else if (ccb_target_family(ccb) == CCB_ARCH_FAMILY_RISCV) {
ccb_target_gen_emit("sext.w a0, a0");
if (ast->left->ctype->size <= 4) {
ccb_target_gen_emit("sext.w a0, a0");
}
}
else if ((ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_FASM || ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_NASM)) {
ccb_target_gen_emit("cqo");
@@ -1838,10 +1840,14 @@ static void ccb_target_gen_binary_arithmetic_integer(ccb_t* ccb, ccb_ast_t* ast)
ccb_target_gen_emit("div r0, r2, r1");
}
else if (ccb_target_family(ccb) == CCB_ARCH_FAMILY_RISCV) {
ccb_target_gen_emit("%s a0, a0, a1", ast->type == '%' ? "rem" : "div");
//if (ast->type != '%'){
ccb_target_gen_emit("sext.w a0, a0");
//}
if (ast->ctype->size == 8) {
ccb_target_gen_emit("%s a0, a0, a1", ast->type == '%' ? "rem" : "div");
} else {
ccb_target_gen_emit("%s a0, a0, a1", ast->type == '%' ? "remw" : "divw");
//if (ast->type != '%'){
ccb_target_gen_emit("sext.w a0, a0");
//}
}
}
else if ((ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_FASM || ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_NASM)) {
ccb_target_gen_emit("idiv rcx");