Partial maths fix, div/rem operators now work for 32/64 bit code (should be mirrored in fossil...). Some issues may still remain with different combinations of types/signednesses/operators and won't be fixed on x86 as pervasively as on RV64.
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@@ -1826,8 +1826,10 @@ static void ccb_target_gen_binary_arithmetic_integer(ccb_t* ccb, ccb_ast_t* ast)
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ccb_target_gen_emit("signx64x32 r0");
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ccb_target_gen_emit("signx64x32 r0");
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}
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}
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else if (ccb_target_family(ccb) == CCB_ARCH_FAMILY_RISCV) {
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else if (ccb_target_family(ccb) == CCB_ARCH_FAMILY_RISCV) {
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if (ast->left->ctype->size <= 4) {
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ccb_target_gen_emit("sext.w a0, a0");
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ccb_target_gen_emit("sext.w a0, a0");
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}
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}
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}
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else if ((ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_FASM || ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_NASM)) {
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else if ((ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_FASM || ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_NASM)) {
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ccb_target_gen_emit("cqo");
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ccb_target_gen_emit("cqo");
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}
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}
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@@ -1838,11 +1840,15 @@ static void ccb_target_gen_binary_arithmetic_integer(ccb_t* ccb, ccb_ast_t* ast)
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ccb_target_gen_emit("div r0, r2, r1");
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ccb_target_gen_emit("div r0, r2, r1");
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}
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}
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else if (ccb_target_family(ccb) == CCB_ARCH_FAMILY_RISCV) {
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else if (ccb_target_family(ccb) == CCB_ARCH_FAMILY_RISCV) {
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if (ast->ctype->size == 8) {
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ccb_target_gen_emit("%s a0, a0, a1", ast->type == '%' ? "rem" : "div");
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ccb_target_gen_emit("%s a0, a0, a1", ast->type == '%' ? "rem" : "div");
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} else {
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ccb_target_gen_emit("%s a0, a0, a1", ast->type == '%' ? "remw" : "divw");
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//if (ast->type != '%'){
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//if (ast->type != '%'){
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ccb_target_gen_emit("sext.w a0, a0");
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ccb_target_gen_emit("sext.w a0, a0");
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//}
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//}
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}
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}
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}
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else if ((ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_FASM || ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_NASM)) {
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else if ((ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_FASM || ccb_target_asmfmt(ccb) == CCB_TARGET_ASMFMT_NASM)) {
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ccb_target_gen_emit("idiv rcx");
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ccb_target_gen_emit("idiv rcx");
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}
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}
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